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半导体电路设计IP及配套交付件

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LVDS / FPD link Rx IP

概述和功能介绍

A physical layer IP for LVDS Receiver. This IP consists of 20-lane (4 x 4D1C) LVDS receivers, and supports up to 1.5Gbps data rate. The input clock is 25MHz to 150MHz. The serializer is highly integrated and requires no external components. The circuit is designed in a modular fashion and desensitized to process variations. This facilitates process migration, and results in a robust design.

LVDS-FPD-link-Tx-IP-supplier-in-europe

 

功能描述
  • LVDS compliant Rx
  • 4 groups of 4-Data, 1-Clock channels
  • Each lane/group can be turned on/off individually
  • Supports from 168Mbps to 1.5Gbps data rate
  • Configurable analog characteristics
  • Bias voltage/current
  • DLL characteristics
  • Testability Internal analog nodes can be observed through a test pad DLL test mode Process
  • Supply Voltage 1.8V/0.9V

Deliverables

  • Datasheet
  • Integration guideline
  • GDSII or Phantom
  • GDSII Layer map table
  • CDL netlist for LVS
  • LEF Verilog behavior model
  • Liberty timing model DRC/LVS/ERC results
Benefits
  • Testability
  • At speed test by Loopback BIST
  • Internal analog nodes can be observed through a test pad
  • Supports VCO gain test, transmitter DC test, IDDQ test
Applications
  • Smart Phone
  • Tablet
  • PC
  • Car navigation
  • Smart TV
  • Digital Still Camera
  • HD Camera

 

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