概述和功能介绍
The Analog TV Demodulator and Decoder IP core is extracted from a production chip and a silicon-proven IP core. The Analog TV demodulator and decoder are two separate blocks of IP cores available as a single license. The input to the demodulator is digital I/Q LIF or Baseband, the input sample rate is customizable to meet the ADC requirement.
The Analog TV Decoder IP contains a high-quality front-end video circuit for processing all analog NTSC/PAL/SECAM standards into a 4:2:2 YCrCb digital video format as well as conventional analog RGB or YCrCb signals. The programmable through an I²C interface.
The provides a cost-effective solution for digitized TV, LCD TV/monitors, digital TV, STB, video surveillance security, video conferencing, video capturing devices, and PC video card.
The Analog TV Demodulator IP provides support for PAL, NTSC, and SECAM. The all-digital implementation is suitable for integration into digital demodulators and digital SOC devices. The solution covers worldwide TV standards, this IP core block also extracted from production SOC.
The input to the demodulator is digital I/Q at baseband at a 19.33 Msps sample rate. The input sample rate is customizable to meet the requirement and changes to the sample rate will require modifications to the filter chain.
For supporting an IF input, the IF frequency is customizable to meet the requirement. For IF inputs, phase rotation to baseband is accomplished by the “Freq correction” block at left using direct digital frequency synthesis (DDFS).
功能描述
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Worldwide TV standards compatible
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Automatic NTSC/PAL/SECAM digital chroma decoder
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NTSC/PAL adaptive 4H/2D comb filter
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VBI data slicer for Teletext, closed caption, WSS and other systems
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Analog RGB/Fast blanking capture and insertion in YCrCb output flow (SCART legacy)
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Analog YCrCb inputs with tint control
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10-bit, 30-MSPS ADC for Y/CVBS input
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8-bit, 30-MSPS ADC for C and RGB/CrCb inputs.
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Hue control and automatic flesh control for NTSC CVBS/YC signals
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Programmable horizontal scaling (x0.25 to x4 scaling factor) and panorama vision
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Copy-protection system compatible
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H and V synchronisation processing that is robust to non-standard sources such as VCR, and to weak and noisy signals
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8-bit pixel output interface line-locked ITU-R BT_656/601 or square pixel YCrCb outputs
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Single system clock for all video input format
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Two-wire I²C bus interface up to 400 kHz
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Typical power consumption: 550 mW
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Power supply: 1.8 V and 3.3 V
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All-digital Verilog RTL Implementation
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PAL Support
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NTSC Support
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SECAM Support
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19.33 Msps, 14-bit baseband digital I/Q Input
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Customized as required
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Carrier Recovery
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Vsynch detect to Change Gain Synchronously
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Rotation to Baseband
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Raised-Cosine VSB Filter
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Complex Filtering to Baseband
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Separation of Video and Audio
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Audio Filtering High Pass Filter (HPF)
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Video Filtering Low Pass Filter (LPF)
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I2C Interface for Configuration
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19.33 MHz Digital System Clock
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Customized as required
Benefits
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Silicon Proven IP core
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Ready to license with Modifications rights, unlimited usage
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Pre and post engineering sales support
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Two separate blocks Demodulator and Decoder
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Complete package
Applications
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CRT TVs
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LCD TVs
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Digital TV
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STB
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Video Capturing Device
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PC Vdo card
Deliverables
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Customization: Input sample rate per customer requirementm, Filter modifications per customer requirement and input sample rate Datasheet
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System Architecture Design Document
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Synthesizable Verilog RTL
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RTL Test Bench and Test Vectors
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Integration Support: Performance Analysis Support, Synthesis and Timing Closure Support
