概述和功能介绍

The Low-Voltage Differential Signaling Transmitter IP Core provides a very High speed and Low power differential data transfer for Video interface and advanced Chip to chip interconnection. With a 400Mbps – 2.5Gbps per-lane data rate with up to 16 transmitter and receiver lanes with shared PMU, the LVDS Tx IP Core is a standard for high-speed video data transfer.

功能描述

• Wide-range data rate, up to 1Gbps, the associated clock is DDR clock (1/2 of the data rate, up to 500MHz)
• 16 channels with a total of 128 bits of parallel data, each channel has a bit width of 8 bits
• DC coupling mode  Multi-channel shared offset
• Built-in transmitter terminal impedance, no need for off-chip components
• Support AXI stream bus protocol and data transceiver
• Built-in self-test mechanism, which can independently complete feature and mass production testing
• Support link training mode
• Support Flip-chip package form
• ESD: HBM/MM/CDM/Latch Up 2000V/200V/500V/100M