经过生产验证的,复杂的半导体IP核

半导体电路设计IP及配套交付件


T2M XPHY Low power Chip to Chip SerDes IP

XPHY Low power Chip to Chip SerDes IP

概述和功能介绍

These IPs are targeted at applications requiring high speed, high bandwidth, low-power consumption, and low-latency interfaces.

Low-Power-Chip-to-Chip-Serdes-silicon-proven-ip-core-supplier-in-europe

 

功能描述
  • Low Power Chip-to-Chip SERDES
  • From 10Gb/s to 11Gb/s
  • Technology: 28FDSOI 8ML & 10ML
  • Platform: 1 Data Slice and 1 Clock Slices
  • RX: AC or DC coupling with low-power CTLE
  • TX: Power-optimized resistive bridge driver
  • Optimized for Low Power Chip-to-Chip SERDES Applications
Benefits
  • Ultra low voltage operation
  • Optimized for low power Chip to Chip SERDES Applications
Applications
  • IOT
  • Wearables