概述和功能介绍
The multi protocol SerDes PHY consist of Peripheral Component Interconnect Express (PCIe) compliant with PCIe 4.0, 3.0, 2.0 Base Specification with support of PIPE interface spec, and JESD204B compliant. Lower power consumption is achieved due to support of additional PLL control, reference clock control, and embedded power gating control. Also, since aforementioned low power mode setting is configurable, the PHY is widely applicable for various scenarios under different consideration of power consumption.
功能描述
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Multiple lanes transceiver with data rate from 1Gbps to 16Gbps
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Transceiver version including both receiver and transmitter
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Transmitter only version
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40bit/32bit/20bit/16bit selectable parallel data bus
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Independent per-lane power down control
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Programmable transmit amplitude
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Programmable 3-tap feed forward equalizer(FFE)
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Embedded receiver equalization (CTLE and DFE) to compensate insertion loss
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Flexible reference clock frequency range
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Integrated LC-tank PLL and Ring OSC PLL
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Fractional-N PLL
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Support spread spectrum clock up to 5000ppm
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Low capacitance ESD structures
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Integrated on-chip differential 100 ohm termination for clock Receiver,TX and RX
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Termination resistance auto calibration function (optional)
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AC coupling
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Support both Flip Chip Package and Wire Bonding Package
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Testability
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High Testability
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Built-in pattern generator and checker including PRBS
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Internal serial loopback
Deliverables
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Application Note / User Manual
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Behavior model, and protected RTL codes
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Protected Post layout netlist and Standard
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Delay Format (SDF)
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Synopsys library (LIB)
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Frame view (LEF)
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Metal GDS (GDSII)
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Test patterns and Test Documentation
Benefits
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Reliability
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Life Time : 10 years
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Life Time Average Temperature : up to 110 degC (include hot-spot)
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Availability : 100%
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ESD (HBM) : over 2000V
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ESD (CDM) : over 250V
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Latch-up : Satisfy JESD78 ClassII (Tj=125c), >100mA
Applications
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PC
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Television
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Data storage
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Multimedia Devices
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Recorders
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Mobile devices
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GPU
